To reduce signal delay and improve electrical performance in high speed integrated circuits, low-k dielectric materials (having a dielectric constant less than 3.9) are often implemented for the intermetal dielectric (IMD) layers of an integrated circuit chip. Low-k and ultra low-k dielectric materials are currently preferred for use in the IMD layers to reduce RC delay and parasitic capacitances. The general trend in IMD designs is that the dielectric constant (k) tends to decrease from the top downward toward the substrate. However, as the dielectric constant (k) decreases, typically the strength of the dielectric material decreases (as a general rule). Hence, many low-k dielectric materials are highly susceptible to cracking or lack strength needed to withstand some mechanical processes (e.g., wire bonding, CMP, lead-free packaging, cutting chips from wafer). Not only do low-k dielectric materials tend to be relatively weak in compression strength, they also tend to be weak in adhesion strength and shearing strength, which can cause peeling, chipping, or delamination.
Typically, the integrated circuit chips are electrically tested prior to cutting the chips from the wafer. Defective chips are marked. It is typically more efficient to test the chips before cutting them from the wafer because many chips on a wafer can be tested at one time using a probe card having an array of probe needles (e.g., to perform continuity tests).
In a conventional method of cutting integrated circuit chips from a wafer, typically cuts are made by a saw blade (e.g., diamond tip) along the cutting streets (also known as scribe lines) between chips on the wafer. During such cutting, low-k dielectric materials often suffer damage such as chipping, peeling, shearing, interlayer delamination, or cracking. However, such damage from cutting the chips occurs after testing the chips. Hence, it is important for reliability and increased production yield to eliminate or significantly reduce the number of chips damaged during a chip cutting process.
During subsequent packing processes after the chips are cut, there are many mechanical and/or thermal stresses exerted on the chip. For example, many packaging designs are moving toward or now use lead-free solder and/or lead-free balls/bumps. A lead-free packaging process will generally exert more stress on the chip than a high-lead package would due to higher reflow temperatures and more rigid lead-free ball/bump material. And at the same time, the IMD layers are using low-k dielectric materials with lower dielectric constants, which are typically weaker and more easily damaged. Any chips, delamination, cracking, or peeling of the IMD layers may spread and become larger during subsequent packaging processes. Thus, there is a great need for methods of cutting integrated circuit chips from a wafer while exerting less stress and/or causing less damage to the low-k dielectric layers (e.g., IMD layers).